PURPOSE:To shorten an interval between a basic cell and a basic cell and to improve integration density, by providing semiconductor regions having the same conductivity as that of a semiconductor substrate or a well region on the surfaces of the side parts of cell lines on the semiconductor substrate or the well region. CONSTITUTION:In basic cell lines 8, n<+> type semiconductor regions 12 are formed on the surfaces of n-well regions n-Well. The n<+> type semiconductor regions 12 are provided on the side parts of the basic cell lines 8 on the side of a wiring region 9. The regions 12 are extended in the same direction of the basic cell lines 8. Each n<+> type semiconductor region 8 is connected to a wiring 7, and a power source potential Vcc, i.g., 5 V, is applied on the n-Well region n-Well. Since each n<+> type semiconductor region 12 is not provided between basic cells 8A and 8A, it is not required to feed the power source potential Vcc to the n-well region n-well between the basic cells 8 and 8. The length of each basic cell 8 can be shortened. Therefore the integration density can be improved.